Jeroen de Coster, Erik Jan marinissen and Joris van campenhout of IMEC; and formfactor, Inc. Bryan C. bolt.
In the past few decades, the computing power and memory capacity of logic chips have increased exponentially. As a result, the demand for input / output (I / O) bandwidth follows a similar trend and now requires terabytes of I / O aggregate bandwidth per second at the chip level. Silicon (SI) photonics is a promising technology to provide such a large I / O bandwidth, especially for applications requiring long-distance interconnection. Using silicon technology, high-performance optical transceivers can be manufactured, combining passive components (such as waveguides and optical filters) and active devices (such as photodiodes and modulators) on a single silicon chip.
The economic feasibility of optical interconnection depends on the cost of optical transceiver to a great extent. The use of Si photonics provides a way to reduce the manufacturing cost of photonics components, because existing CMOS infrastructure and processing technology can be utilized. However, like all microelectronic products, optical transceivers need to be tested for manufacturing defects before they can be sent to customers at an acceptable level of quality.
Testing the active and passive components of integrated Si photonic circuits will greatly reduce the cost of optical links. In general, manufacturing tests have been performed at the wafer level to prevent packaging costs for known bad devices, which are also expensive. For Si photonics in the stage of technology development, these tests have been carried out by manual test station. However, as the number of optical I / O devices is increasing, it is necessary to (semi) automate wafer level test stations to speed up the development and production of optical links.
In order to illustrate the requirements of such (semi) automatic test stations, we take the Si photon platform of IMEC as an example. It aims at the telecommunication and data communication industry, integrating various passive and active components together. In addition to developing specific process modules, IMEC has also established a library with standard components. However, to ensure predictable, stable, reliable and cost-effective library components, efficient and automatic wafer level testing functions are required. These functions must provide accurate and fast feedback on equipment performance to process engineers and optical component and circuit designers.
Flexible test setup
IMEC and formfactor have developed a photonics test station that can semi automatically characterize passive and active Si photonic devices at the chip level (200 mm and 300 mm chips). In the semi-automatic test station, a single wafer is loaded manually, and then the detector automatically crosses the wafer.
The system is a semi-automatic built-in φ 300 mm probe table around the size specification of cascade pa300, equipped with RF probe manipulator and two motorized fiber manipulators. These optical fiber manipulators can measure any combination of light port and electric port in the photon circuit. For passive devices such as FBG couplers, waveguides, and filters, the optical transmission spectrum can be measured. For active devices such as photodiodes and modulators, electrical parameters (at DC and RF frequencies) and electro-optical parameters can be measured.
Figure 1 - schematic diagram of two electric optical fiber manipulators installed on the platen of the cascade pa300 semi-automatic probe table of formfactor.
The challenge of developing photon wafer probe table
The development of wafer level photonics test hardware is a new application for test equipment manufacturers, and faces a series of challenges.
First, optical testing at the chip level requires a method for effectively coupling light from, for example, a single-mode fiber to an optical circuit on a chip. The well-known method is to use a fiber grating coupler, which allows out of plane optical coupling between the waveguide on the wafer and the single-mode fiber. In order to minimize the coupling variability, it is necessary to align the fiber and the FBG coupler accurately and firmly before each measurement. Secondly, the shape of the chuck used to fix the wafer is very important in the test process, because any non planarity will affect the measurement results.
Finally, dealing with unwanted fluctuations and achieving high quality, consistent data sets from wafer to wafer (or batch to batch) is a major problem. The data is easily affected by the polarization change of the incident light (caused by the movement of the optical fiber) or the insertion loss (or signal power) change at the optical fiber connector. Therefore, monitoring and ensuring the short-term and long-term repeatability of measurement results is a key requirement.
Coupling light to light path
The team uses a single-mode fiber and a fiber grating coupler to couple light from the fiber pigtail to a circuit on a chip. The single-mode fiber is almost perpendicular to the surface of the wafer and located above the fiber grating coupler on the wafer. In this way, light is collected and directed into a waveguide on a chip. However, any misalignment of the fiber relative to the FBG coupler will cause additional insertion loss during optical measurement. Therefore, an automatic fiber alignment program has been developed to achieve accurate alignment. This routine is based on finding the optimal transmission optical power during the scanning motion of the optical fiber along a predetermined path. The proposed fiber alignment program can achieve stable fiber alignment less than 0. The change of optical insertion loss from fiber to wafer is 07 dB (+ / - 3S). This alignment step should be applied before each measurement.
Fig. 2 is a schematic diagram of a single-mode fiber located above a fiber grating coupler. The fiber is 10 degrees from the vertical. Light is incident into a 10 micron wide waveguide on the chip.
The influence of the shape of wafer chuck
The team also evaluated the effect of chuck morphology on optical measurement. For example, any nonplanarity in a chip chuck (for example, the
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